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7 Threads found on edaboard.com: Vhdl And Asic And Library
Hello everyone, I'm new in the digital world. I'm looking how I can generate a vhdl file representing the cells of the PDK library. In brief, I've a RTL/vhdl code I synthesis with LeonardoSpectrum. I want now to perform a post-synthesis simulation and put back the synthesized vhdl in (...)
From the Synopsys library Compiler manual: The library Compiler tool from Synopsys captures asic libraries and translates them into Synopsys internal database format for physical synthesis or into vhdl format for simulation.
hi friends. iam working in leonardo spectrum for vhdl synthesis as part of a digital asic project.I got the tsmc 018um from mentor adk. i have loaded the library and its working fine. I am using the netlist in tanner SPR. I have a small problem here. The tanner SPR is not doing automatic mapping. The reason (...)
i have a vhdl project which i want to synthesize.........i need some tool to synthesie logic from it and map it onto a .35 um standard cell library which i have.......can anyone suggest me some free tools for asic logic synthesis.........also i want some free tools for place (...)
you can use the common "+" statement to indicate it is a plus operation, and use according synopsys directive statement in your vhdl comment, then DC will call the DesignWare library cell to do it
I have synthesized this vhdl code for RAM in a Xilinx FPGA
vhdl code must synthesize to gate level netlist use someone asic vendor library. but now there are not have free EDA software