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1000 Threads found on edaboard.com: Vhdl Codes
You may call it a device specific problem. But a very general problem if you don't find any logic device that has double edge sensitive FFs. As you found out, it's possible in simulator, hence no vhdl syntax or semantic problem. However, legal vhdl isn't necessarily synthesizable.
Your question isn't very specific, what do you want to achieve? vhdl and Verilog are digital simulators without means to represent analog signals or sources. I can imagine a discrete noise generator as part of a digital signal processing test bench, it could e.g. use the pseudo random function UNIFORM() in IEEE.MATH_REAL and possibly digita
I would like to know if there are good (preferably open source) vhdl synthesis tools for educational purpose. It doesn't matter if they can not program a device. I know it doesn't look very professional, but Quartus and Vivado (or ISE) are very huge. They easily fill more than 5GB of disk. I tried Quartus lite (1.5GB installer) and the unpacked siz
Recently downloaded a memory model for DDR4 memory from micron's website and found that they have converted their models into System Verilog Interfaces. I'm ok with that... however, I still need to put a wrapper around it to make it work with mixed vhdl/Verilog-2001 simulation. I'm not really sure how to correctly connect the inout ports from
Hi to all, Ok, I have discovered that a my function work when I do: function myConvert (A : in STD_LOGIC_VECTOR( 7 DOWNTO 0 ) ) return integer is variable output : integer := 0; begin output := 5; return output; end function; But, it do not work when I do: function myConvert (A : in STD_LOGIC_VECTOR( 7 DOW
Hi, I need to send data from PC to COM port continuously which is just a short string to be send every 10 second. Is it possible to write for loops in Tera Term for that purpose ?
Hello All, Looking how a latch can be generated in Verilog/SV, normally the following case is cited: - use of always@(*) where not all "reg" are updated (normally in cases where you have an "if" condition without a "else" condition when making combinational logic) However, I have the feeling that the same condition can be achieved when us
Dear all I have two model of BRAM in verilog. I dont know which of them is more accurate? Could you please check the attached code and tell me which is better? I have attached both of codes in "bram.txt"
A first sight, you are defining signal r_clk_counter : integer range 0 to CLK_BIT-1 := 0; but comparing if r_clk_counter = CLK_BIT then which never occurs. There may be more errors. - - - Updated - - - Also wrong sequence. Output is set to '0' after start bit but s
Hi all; I write a vhdl code below. There are no error when I compile it, but then fatal error occur when I try to simulate. library ieee; use ieee.std_logic_1164.all; entity comparator2 is port ( A, B: in std_l
Hi all; I write a vhdl code below. There are no error when I compile it in Quartus, but then fatal error occur when I try to simulate in ModelSim.
Hi I invented a "shift register" like circuit that behaves similarly to a linear feedback shift register, but it has a complete sequence. From here on I will call this circuit Non-Linear Pseudo Random Generator NLPRG for simplicity. Below some circuit typologies ranging from 3 up to 16 bits ( if you somebody wants I can explain how it works and
Hi guys anyone here can help me to find a binary file to the assembly file (Disassembler program) for the MC68020 (68000 series) Motorola processor. Thanks a lot
I want to accelerate CIFAR-10 dataset on a Virtex 5 FPGA. I think I have built correctly the CNN on vhdl. My question is how I load the dataset on the FPGA? Or should I send the images through another device/laptop on the FPGA? I thought also of using SPI/I2C/UART/Ethernet but seems this makes a bottleneck? Right? Also, could it be better to store
I want to start a simulation with Verilog BSIM-CMG 110 but when I run example codes of the model I get an error " *pvaE* Please invoke hspice script instead of binary. " How can I solve this problem? thanks all
You are using incorrect terminology in your posts, so your questions don't make any sense. What you have shown for your vhdl code is a simple divide by 2, 4, 8, and 16, with another divide by N/2 output. Your scope traces have no information on what they represent so are useless. Not knowing what they mean all I can say is that you are probab
"=" is the equals function. It is in double quotes because it is one of the vhdl default operators, and "=" is implicity defined for all types in the package the type is decalred in. The fact it has a . infront of it means it is being pull directly from the cpu_types package, and it is being called explitly like a normal function. There is no a
Help identify the item. Used in the attenuator of the HM8135 generator. 77 package. Thanks. 158620
This is not how generic types work. a generic list can have a type as a generic. But internally you do not have any knowledge of that type. Hence you cannot get access to the default value, because it doesnt exist. package record_pkg is type myType is record myValue : integer; end record; end package; package GenericPkg is
Is it possible to build a CNN on Matlab and transform it to vhdl code? Has anyone experience on this? Thanks... Generating vhdl code from matlab requires the paid for HDL coder feature.