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127 Threads found on Vhdl Display
I have generated a VGA signal, and succeeded to draw a rectangle. I have also code for ROM designed using vhdl, and initialized with a file that has patterns. I'm beginner in vhdl and FPGA. I would like to read the contents of the ROM and use the VGA generator to display the contents. here are the codes. LIBRARY ieee; USE ieee.std_log
For loops are unrolled in synthesis to create parallel hardware. vhdl is not a software langauge, loops are not temporal.
Hi I am new to vhdl and this is my first post. I am trying to connect to a led display which require a certain start up sequence of the signals Let say I have 3 signals a,b and c. I want the signals to go high with 3 us delay each. How can this be done? I have tried something like -------------------------------------- s
Im guessing you're talking about verilog, as in vhdl this happens automatically. In SystemVerilog - try using a enumerated type: typedef enum {STATE1, STATE2} state_t; Otherwise you need to use TCL commands to create a custom radix to display a given name. See "radix define" in the model reference manual:
I'm doing a school proyect that I need to finish pls help! I need to calculate the histogram en code vhdl of an grayscale image 128*128. The input image is received via RS-232 from Matlab to FPGA Spartan 3E(xilinx), and must be stored in BRAM ipcore or 2d-ram (can be an external SRAM also i hear from the board). The histogram obtained is shown
The easiest way is hurray to bring it out via normal port mapping. With verilog and vhdl 2008 you could use hierarchical signal names to get the signal
can you please provide the verilog code for the seven segment display interfacing with the spartan-3 fpga which has 3 digit display.this below link show you the kit .
if initializaton of lcd means entry mode set, display on display off , clear display , all this , then i have done it .. will u plz explain once more . The problem is you've written your code as a "program" (like in software with delays). In vhdl you write a description of hardware (i.e. a text description of the l
Hi Guys, we are having a doubt to interface with VGA using DB15 connector it having the input and output pins of hsync, vsync, red, green, blue, all will be single bit,. we are given hsync and vsync properlly, but the problem is how can we are given data to this device, because we are converting the jpeg image to hex format, and loaded that data
Hi there, I am trying to interface a HEX keypad with to display the key pressed on seven segment display. I am new to HEX keypads. I have read some theory about HEX keypads. But I am unable to make the decoder. Can anyone pls provide a sample code for it in vhdl (I am OK with seven segment displays). Thanks. Emma Good.
Sorry but I still don't understand. wcycle and rcycle are tested to assert full0 and empty0 and you tell me they're not required. Why? And you tell I can read and write in the same cycle, not before. Explain the difference. You didn't tell me why the precedent version was wrong. I thought I could easily understand vhdl but it seems I'm not! Explain
Hello all, i have a testbench written in verilog that does the following: initial begin $display(" ") ; $display(" !!!!!!!!!! Starting Tests !!!!!!!!!!"); $display(" ") ; $display(" ") ; $display(" ") ; $display(" ") ; (...)
Hellow Everyone, could any one post me spi slave code in vhdl by using cpol and cpha? I have written one code but my slave code is able to receive data from master but the miso doesn't have any data. The slave receiving data also not perfect some times some random data is receiving like with bit shifting. Following is my slave code --------
Hello, I am new to FPGAs and LCD devices. I am trying to interface an LCD device with a Spartan 3 kit (LCD module - 2 line-pre connected in it). Does anyone have a basic vhdl code to display a single character / word on the LCD panel. I am finding the codes available here and on the net complicated to understand. Also, what is CGRAM and DDRAM
how to initialize lcd in vhdl ! with the boring détails i searched about it ! but I didn't understand how it works
Hello friends Its the first time for me to deal with LCD, now I am trying to display some data on the LCD of the spartan 3e starter kit from xilinix. I do need your help to let me start dealing with LCD using vhdl. I need any material to read about,, a simple codes to get start, any help will be very appreciated. Thank you and I am looking fo
Hellow all I need vhdl code for the Glcd 128x64 jhd128x64. i m using cpld krypton board please help me to give jst character display code for that. thank you regards anthony mario.
sLeds <=conv_std_logic_vector(tState'pos(sMainState), sLeds'length); And here is how to do it with the standard library numeric_std: sLeds <= std_logic_vector(to_unsigned(tState'pos(sMainState),sLeds'length));
Hi, I need to implement a circular buffer in vhdl I have 2 signals which I need to display on seven segment (3 digit number using 3 sevensegment) I need to display a different characters on 4th seven segment for each signal value And how can I display them circularly Thanks xilinx1001