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import spice , import cadstar , import lef , lef import
46 Threads found on edaboard.com: Vhdl Import
I would really appreciate your help. I wrote the following testbench code to test my 6th order FIR filter. It worked perfectly for my behavioral code, but when I try to use it after synthesis for my structural gate-level netlist, I get this error: ERROR:HDLCompiler:1728 - "/home/..." Line 24: Type error near xin ; current type signed; e
Hi. I'm trying to import vhdl source code into Verdi. The source code included user-defined-library file like this library ieee, ZOTLIB ; use ieee.numeric_bit.all ; use ZOTLIB.COMPONENT ; ... The error messsage is like this Can not find library. How can I import library?
Hi Folks, I would like to perform matrix multiplication in vhdl,I have to save the end product in RAM. Thanks in advance.
Maybe you can import vhdl/verilog netlist (synthesized by DC or other tools) directly into virtuoso environment. Then a new schematic will be generated and can be used to do further simulation in ADE. Regards,
Hi, I'm looking for a way to convert a Behavorial description (in vhdl or VERILOG) into a (H)SPICE netlist. I did it in the past with tools from Cadence, but in my current situation I can only use tools from Synopsys. I've tried to look into Design Compiler / Nanosim but I couldn't find anyway of doing that. Is there any other software to do
Information in this page suggests that a function declaration is optional... . The link doesn't talk about packages at all, just functions in general. I see that it doesn't fail a parsing check... Did you also try to import the function in your design? I presu
Ususally, circuits are written in HDL, and often in behavioural form. There is no way to input a K map, just the circuit diagram (which people dont use much, as it cannot be simulated directly). It is much better to use an HDL (vhdl or Verilog).
Alternatively you can build your ISE projects from a Makefile. Then add a rule to update the vhdl file with date & time in it. Essentially it's the same mechanism as that tcl example ... generate a vhdl file with datetime in it.
c <= ('a(3)'&a) + ('b(3)'&b);--to make sign extension. You can also write c <= resize(a,5) + resize(b,5); or even shorter c <= resize(a,5) + b; What I'm doing is because vhdl imposes that the LHS to the equal sign of addition is the same size as the RHS' operands. Will this concatenated bit be r
You will have to existing standard cell library to which you vhdl/verilog code synthesizes to. Once you import the gate level netlist into cadence it needs to map to the actual gate which should exist in the cadence library(if you have one). Once you get the library, then you dump the netlist and layout from the standard cell library. Usually peopl
i have a vhdl code ...and we have standard cell in cadence in the front end. How can i import vhdl CODE into cadence and link it with standard cells and simulate it? Pl Help
Hi fellow forum members, As the title suggests, I need to read data from a data file, get the integer values, convert them to two's complement binary and use them as inputs in my vhdl design. My goal is to build a basic signal generator via BASYS2 board and DAC. My plan is to use matlab as an ideal signal sampler, get the functions' values(squar
Hi, is there a way to simulate a vhdl project created in quartus with ISIM of xilinx? I can't compile it in xilinx because it uses pll and other specific functions of altera. Thanks
Hello,I want to import an array (1 x n) to my vhdl code,every element of array is 5-bit.I know I should be use it in serial but I dont know how define input "std_logic or std_logic_vector(4 downto 0)?
I need to import data generated from matlab into vhdl program and then execute and get results exported into matlab for further analysis. how can I do it?
library ieee; use ieee.std_logic_1164.all; entity updowncounter is generic (n: natural := 8); port ( IC,CLK,upcount,downcount :in std_logic ; Q: out std_logic_vector(n-1 downto 0) ); end updowncounter ; architecture exm1 of updowncounter is begin prc:process (IC,CLK) is variable cnt : unsigned (n-1 downto 0); -
I think you are asking for For vhdl the procedure is the same but you select the vhdl folder and files.
Does Modelsim support use of fixed point? It's no Modelsim problem, the libraries are just vhdl code. Apparently you didn't import the libraries to the simulation project. The altera simulator can only do post place and route simulation. Not quite right. The internal Quartus simulator (available up to V9.1) suppor
I import a vhd file in candece like following: Open icfb. Go to file choose import and then vhdl. Under the file name browser in the vhdlin form go and select the inv vhdl file hit the Add button on the right hand side of the browser window. In the Target Library Name field (...)
I have a synthesised vhdl file with TSMC 180 nm library using Synopsys Design Vision. Now,I want to have the schematic using Cadence Virtuoso.How to do that ?