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78 Threads found on edaboard.com: Vhdl Processor Code
You can do it with a 3rd party pre-processor that generates a new file from a template. At one point I had one that let me embed python code in a vhdl/Verilog file for the purpose of code generation. Yes, you can do that. But I presume the thread topic is learning valid vhdl syntax rather than using a (...)
A straightforward way could be to implement a small soft processor in FPGA and write the AT command handling in C language. Of course it's possible in pure vhdl as well, but no fun particularly. Some necessary steps: - write the RX and TX UART code - write a command state machine to send specific AT commands - write a parser to (...)
Hi, I'm trying to run my first code on ARM Cortex-M1 soft processor. It is quite complicated process for me and there are many steps where I could make some mistake. But now I have: 1) vhdl project and bitstream loaded into ProASIC3L FPGA, 2) simple C program to turn on one LED connected to GPIO output. But when I try to run it in (...)
Hi, When i write a code in vhdl, I want to know in which memory location this code goes and gets stored using Vivado for Zynq. How will i come to know this address location using the tool? I am designing a RAM and want to specify the start and end location where one can come and store the data. This is why i need to know the address.
HI, I have a 14-bit data that is fed from FPGA in vhdl, The NIos II processor reads the 14-bit data from FPGA and do some processing tasks, where Nios II system is programmed in C code The 14-bit data can be positive, zero or negative. In Altera compiler, I can only define the data to be 8,16 or 32
I designed a 5 stage pipelined RISC processor in vhdl, synthesized the code using ARM libraries on 65nm Technology using synopsis Design Vision Tool. Also, post synthesis simulation is correct. At the place and route stage, i am using IC Compiler (Synopsys).. However , no matter what i do, i get Zero DRC errors, however 2 LVS errors ( 2 (...)
I know on some Xilinx forums this question was already discussed and conclusion is 2 layer PCB with Spartan 6 is asking for problems. I have project where is ARM processor and also needs some "fast" state machine to handle operation. I have wrote and tested preliminary version of vhdl code, it uses about 100 flip-flops and fit inside larger (...)
Im working design 128point fft processor design in schematic using xilinx Pls help me to design for 128 point fft processor design need vhdl code
Hi, I want to know that is it possible to convert verilog or vhdl to other processor's assembly code(such as Intel) ?? is there any special converter?? tnx
i want to send data from fpga de2-70 kit to usb flash drive. i do not know how to start can you please help me
ERROR:HDLCompiler:1731 - "C:/Xilinx/processor/alu32.vhd" Line 87: found '0' definitions of operator "=", cannot determine exact overloaded matching definition for "=" =================================================== I am getting this error on all of the lines with "=" I am using a case and here are the lines where the error comes up: [synt
Does anyone have vhdl code for simple processor with 4 4-bit registers and a 16- word memory with 8-bit words.
hi im trying to make an image processor using virtex5, and im using modelsim for simulation tool. my question is, in testbench file, how to read multiple sequential images? i can open and read 1 frame image but dont know how to do when the next frame is needed. this is part of my test bench code .... initial begin
I'm no vhdl expert but this isn't the standard way of implementing a behavioral flip-flop. signal sig_internal: std_logic_vector (31 downto 0):= (others => '0') ; begin process ( clk , pc_in ) begin sig_internal <= pc_in ; if (rising_edge(clk)) then pc_out <= sig_internal ; end if; end process ; I'm not entirely
What is the Logic in your vhdl code to control the LEDs ? I hope that you have assigned LED pins in UCF. What is the architecture or flow of your logic in simple ?
hi to all, I've tried to add a new source in ISE 14.2, for a vhdl project. but I faces this error in any situation: "Path with spaces is not supported in XPS. Please choose a path with no spaces" the directory which I have created does not have any spaces. I even try to add it in a path like "d:\" but the problem was not solved.
Hi Friends I am not good in vhdl , i need explanation of tb_msp.vhdl file in leon2 processor I need to modify the code for my project, if I understand the concept, it will help me to modify it. please help me friends it is the link for tb_msp.vhd
hi all, can anyone has code for embedded dsp processor design using vhdl,MATLAB or LISA....I am doing a project on design of the processor first time.so,i need some proper approaches to write the code.so,please help me......if anyone had please mail to me.......
Please anyone have the vhdl code for split radix fft algorithm using cordic processor.please post it.
see the example at EMBEDDED SOPC DESIGN WITH NIOS II processor AND vhdl EXAMPLES chapter 17 (2011 ed)