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Vhdl Real Type

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40 Threads found on edaboard.com: Vhdl Real Type
Hello, Does vhdl have a native 2's complement negation function for signed vectors ? I.E - a function that takes a signed vector, flips it and adds '1' to the LSB ?
Hello, I'm trying to design a generic synthesizable SINE LUT in vhdl. I'm using the "real" type to compute the LUT's values during compile time. This is my code: library ieee ; use ieee.std_logic_1164.all ; use ieee.numeric_std.all ; use ieee.math_real.all ; entity sine_lut is generic ( (...)
What happens when the Left side is "real" and the right is "unsigned", What happens when the Left side is "signed" and the right is "real"...etc. I wonder in which situations the combination would be required in synthesizable vhdl? real is only applicable for compile time calculations, e.g. initialization of constants (...)
Hi everybody, I'm trying to compile this vhdl program in Quartus, but there is an error when I compile it : Error (10414): vhdl Unsupported Feature error at filehandle.vhd(14): cannot synthesize non-constant real objects or values This error message is on this line : signal dataread : real; These VHLDs co
Hello, x is defined as: signal x: std_logic_vector ( 7 downto 0 ) ; I want 'x' to be incremented by 1 with relation to the simulation time - for example: "00000000" at time: 10 ns "00000001" at time: 20 ns "00000010" at time: 30 ns The obvious will be: x <= "00000000" after 10 ns , "00000001" after 20 ns , "
entity MY_PROG is port( real : in std_logic_vector (31 downto 0); Imag : in std_logic_vector (31 downto 0); realo : out std_logic_vector (31 downto 0); Imago : out std_logic_vector (31 downto 0); clk, Request: in std_logic; ); end MY_PROG ; Is this valid to use "real" as a input port list in the entity as
I have a bit_vector(4 downto 0) and I am trying to convert it to a real so that I may write to a file. dataout <= real(integer(to_signed(std_logic_vector(data)),5)); The error I get is illegal operand for type conversion. I was able to change real to std_logic_vector: datain <= (...)
if you really want to use floating point, you will have to use the floating point cores from your vendor. But I highly suggest you read up on fixed point notation. It is essentially an integer multiplcation with an offset. Either way, you cannot use the real type in vhdl for synthesisable designs.
I guess there are several ways to find the odd or even count values. I have mentioned 1 method in full vhdl code and other 2 methods as snippet. I would like to know other methods to determine these odd or even count values and they should also be synthesizable. Could some one help me on this. Thank you. library ieee; use std_logic_1164
Well RTL code only knows bit/std logic signals, floating point is an abstraction, coded in your std_logic_vector. Floating is only usable with real type in vhdl, and this is not synthesisable, only for test purpose.
but give me this error : No feasible entres for infix operator "/" if use real ( x ) ihaven't erro but my output answer it's wrong ang give me this 4.656661e+298 1. Other than e.g. C language, vhdl doesn't provide automatic type conversion, arithmetic operator can be only applied to the data types they are defined for. 2. (...)
Hi All, Can we use the real expression after WAIT FOR in vhdl. For example, ... signal delay : real; ... delay <= 2.5; ... process begin clk <= '1'; WAIT FOR delay; clk <= '0'; WAIT FOR delay; end process; But wh
hi all, how can i generate a code for fir filter using software other than matlab.. i used matlab but the problem i faced was real variable data type was not supported by the software i use.. pls help me as early as possible.. how to generate a verilog or vhdl code using a software or a solution for the error got for real (...)
Yes. The floating point library at has a to_slv function.
hi , I need to define floating number (which is data type of real in vhdl) ,came to know that real data type is just for simulation purpose and its practically "not synthesizable". so how can I define these floating numbers so when I use FPGA these float numbers are synthesizble thank you in advance
Hi all, Is it possible to convert real to integer type in vhdl?Is there any in-build function to do this conversion?
hi in my vhdl code i`m getting an error saying Xst:1547 - "F:/Xilinx/img_wr1/img_wr.vhd" line 75: Signal of type real is not supported. pls help me to overcome this error as early as possible
You have to remember that a std_logic_vector is not a number, or integer, or signed, or real or any other type of number. It is just a collection of bits. So actually you are not assigning it with a binary number, or hex, it is a string ("00101001", x"FFAA", o"1745" etc..). If you want to assign integers, you need to convert an integer from the in
my input is of format -6.5 or 10.55 Very unlikely, that's just a decimal number string. real is a vhdl type available for compile time calculations and simulation. It's not synthesizable. Standard vhdl libraries are providing only integer numbers (unsigned and signed). In addition, there are proposed IEEE libraries (...)
I don't know Verilog as well as vhdl so its better to post your questions/problems here in this topic. Maybe someone else will know the answer.