Search Engine

Vhdl Real Type

Add Question

40 Threads found on Vhdl Real Type
I'm guessing the types for a and b should be signed from numeric_std? Yes - any standard signed type will work: integer real And from vhdl 2008 sfixed std_logic_vector (when using numeric_std_signed) bit_vector (when using numeric_bit_signed)
Yes you can - define it all in an initialisation function: constant sin_rom : type_lut function define_rom return type_lut_sine_slv is variable ret_rl : type_lut_sine_real; variable ret : type_lut_sine_slv; begin for index in ret'range loop ret_rl( index ) := sin ( (...)
What happens when the Left side is "real" and the right is "unsigned", What happens when the Left side is "signed" and the right is "real"...etc. I wonder in which situations the combination would be required in synthesizable vhdl? real is only applicable for compile time calculations, e.g. initialization of constants (...)
That is where knowing the language by reading the LRM and books helps. I haven't actually seen a comprehensive list of all the vhdl statements that show yes/no/maybe/sometimes synthesizable. If a vendor changes their tool they may add something that is currently not synthesizable. Given that there are some things that will
Hello, x is defined as: signal x: std_logic_vector ( 7 downto 0 ) ; I want 'x' to be incremented by 1 with relation to the simulation time - for example: "00000000" at time: 10 ns "00000001" at time: 20 ns "00000010" at time: 30 ns The obvious will be: x <= "00000000" after 10 ns , "00000001" after 20 ns , "
vhdl reserved words are listed in the LRM. "real" isn't a reserved word. As long as you don't use the predefined real type in your design entity, you can probably use the name for other other objects, e.g. a port name. But why should you? It causes confusion, starting with the syntax highlighter. Somehow a useless discussion.
I have a bit_vector(4 downto 0) and I am trying to convert it to a real so that I may write to a file. dataout <= real(integer(to_signed(std_logic_vector(data)),5)); The error I get is illegal operand for type conversion. I was able to change real to std_logic_vector: datain <= (...)
if you really want to use floating point, you will have to use the floating point cores from your vendor. But I highly suggest you read up on fixed point notation. It is essentially an integer multiplcation with an offset. Either way, you cannot use the real type in vhdl for synthesisable designs.
I guess there are several ways to find the odd or even count values. I have mentioned 1 method in full vhdl code and other 2 methods as snippet. I would like to know other methods to determine these odd or even count values and they should also be synthesizable. Could some one help me on this. Thank you. library ieee; use std_logic_1164
Well RTL code only knows bit/std logic signals, floating point is an abstraction, coded in your std_logic_vector. Floating is only usable with real type in vhdl, and this is not synthesisable, only for test purpose.
but give me this error : No feasible entres for infix operator "/" if use real ( x ) ihaven't erro but my output answer it's wrong ang give me this 4.656661e+298 1. Other than e.g. C language, vhdl doesn't provide automatic type conversion, arithmetic operator can be only applied to the data types they are defined for. 2. (...)
Hi All, Can we use the real expression after WAIT FOR in vhdl. For example, ... signal delay : real; ... delay <= 2.5; ... process begin clk <= '1'; WAIT FOR delay; clk <= '0'; WAIT FOR delay; end process; But wh
hi all, how can i generate a code for fir filter using software other than matlab.. i used matlab but the problem i faced was real variable data type was not supported by the software i use.. pls help me as early as possible.. how to generate a verilog or vhdl code using a software or a solution for the error got for real (...)
Yes. The floating point library at has a to_slv function.
hi , I need to define floating number (which is data type of real in vhdl) ,came to know that real data type is just for simulation purpose and its practically "not synthesizable". so how can I define these floating numbers so when I use FPGA these float numbers are synthesizble thank you in advance
Hi all, Is it possible to convert real to integer type in vhdl?Is there any in-build function to do this conversion?
hi in my vhdl code i`m getting an error saying Xst:1547 - "F:/Xilinx/img_wr1/img_wr.vhd" line 75: Signal of type real is not supported. pls help me to overcome this error as early as possible
well in define of constant constant8: std_logic_vector(15 downto 0) := 20000; the vhdl take error.:sad: what should i do????
Hi all, I am quite new to the ISE webpack & vhdl; i would like to represent an input signal as a floating/fixed point vector. how do i do this. for instance: my input is of format -6.5 or 10.55. How do i define my input ports. port( input : in float(7 downto -4)... something like this.. Hope i have conveyed my intentions. Plz need y
I don't know Verilog as well as vhdl so its better to post your questions/problems here in this topic. Maybe someone else will know the answer.