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Vhdl Real Type

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40 Threads found on edaboard.com: Vhdl Real Type
I'm guessing the types for a and b should be signed from numeric_std? Yes - any standard signed type will work: integer real And from vhdl 2008 sfixed std_logic_vector (when using numeric_std_signed) bit_vector (when using numeric_bit_signed)
Yes you can - define it all in an initialisation function: constant sin_rom : type_lut function define_rom return type_lut_sine_slv is variable ret_rl : type_lut_sine_real; variable ret : type_lut_sine_slv; begin for index in ret'range loop ret_rl( index ) := sin ( (...)
What happens when the Left side is "real" and the right is "unsigned", What happens when the Left side is "signed" and the right is "real"...etc. I wonder in which situations the combination would be required in synthesizable vhdl? real is only applicable for compile time calculations, e.g. initialization of constants (...)
Hi everybody, I'm trying to compile this vhdl program in Quartus, but there is an error when I compile it : Error (10414): vhdl Unsupported Feature error at filehandle.vhd(14): cannot synthesize non-constant real objects or values This error message is on this line : signal dataread : real; These VHLDs co
Hello, x is defined as: signal x: std_logic_vector ( 7 downto 0 ) ; I want 'x' to be incremented by 1 with relation to the simulation time - for example: "00000000" at time: 10 ns "00000001" at time: 20 ns "00000010" at time: 30 ns The obvious will be: x <= "00000000" after 10 ns , "00000001" after 20 ns , "
vhdl reserved words are listed in the LRM. "real" isn't a reserved word. As long as you don't use the predefined real type in your design entity, you can probably use the name for other other objects, e.g. a port name. But why should you? It causes confusion, starting with the syntax highlighter. Somehow a useless discussion.
I have a bit_vector(4 downto 0) and I am trying to convert it to a real so that I may write to a file. dataout <= real(integer(to_signed(std_logic_vector(data)),5)); The error I get is illegal operand for type conversion. I was able to change real to std_logic_vector: datain <= (...)
\\\ prefix of slice name must be an array \\\ vhdl compiler existing ***** i got this two error . i dont know how to solve it. ***** i want to multiply an 8 bit number with 0.1(decimal number) please help me library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mult is port(A : in std_log
I guess there are several ways to find the odd or even count values. I have mentioned 1 method in full vhdl code and other 2 methods as snippet. I would like to know other methods to determine these odd or even count values and they should also be synthesizable. Could some one help me on this. Thank you. library ieee; use std_logic_1164
Well RTL code only knows bit/std logic signals, floating point is an abstraction, coded in your std_logic_vector. Floating is only usable with real type in vhdl, and this is not synthesisable, only for test purpose.
Hi , I want execute this line in vhdl and i have no error but after compile it with Orcad and define the signal .. after RUN i have this error : Run time error accure at time 0 ns : a , b, is real array matrix , c,d just real a(0,0) <= b(0,0) * (c/d) and if you have any idea for improve it , plz tell tanks plz help :?:
Hi All, Can we use the real expression after WAIT FOR in vhdl. For example, ... signal delay : real; ... delay <= 2.5; ... process begin clk <= '1'; WAIT FOR delay; clk <= '0'; WAIT FOR delay; end process; But wh
hi all, how can i generate a code for fir filter using software other than matlab.. i used matlab but the problem i faced was real variable data type was not supported by the software i use.. pls help me as early as possible.. how to generate a verilog or vhdl code using a software or a solution for the error got for real (...)
Yes. The floating point library at has a to_slv function.
hi , I need to define floating number (which is data type of real in vhdl) ,came to know that real data type is just for simulation purpose and its practically "not synthesizable". so how can I define these floating numbers so when I use FPGA these float numbers are synthesizble thank you in advance
Hi all, Is it possible to convert real to integer type in vhdl?Is there any in-build function to do this conversion?
hi in my vhdl code i`m getting an error saying Xst:1547 - "F:/Xilinx/img_wr1/img_wr.vhd" line 75: Signal of type real is not supported. pls help me to overcome this error as early as possible
You have to remember that a std_logic_vector is not a number, or integer, or signed, or real or any other type of number. It is just a collection of bits. So actually you are not assigning it with a binary number, or hex, it is a string ("00101001", x"FFAA", o"1745" etc..). If you want to assign integers, you need to convert an integer from the in
Hi all, I am quite new to the ISE webpack & vhdl; i would like to represent an input signal as a floating/fixed point vector. how do i do this. for instance: my input is of format -6.5 or 10.55. How do i define my input ports. port( input : in float(7 downto -4)... something like this.. Hope i have conveyed my intentions. Plz need y
I don't know Verilog as well as vhdl so its better to post your questions/problems here in this topic. Maybe someone else will know the answer.