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129 Threads found on Vhdl Serial
Hi, guys! I have a simple code to load a serial input. ------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity test is Port ( Dclk : in STD_LOGIC; InputL : in STD_LOGIC; Frame : in STD_LOGIC; rj_L : out
You surely want fixed point rather than floating point arithmetic. Thinking about reasonable number formats and required accuracy would be a first step to approach a vhdl implementation of your problem. Also intended processing speed plays a role, do you need a pipelined parallel divider or can a serial divider be used? I implemented a similar a
Hello which vhdl are you using?
Hi Guys I need your help again. :-) Here is the Scenario of what I want to do : 1- I have and input that is std_logic_vector (N downto 0) and 5serial transmitter. I am going to Discribe that I plan to do, if u have any suggestion, tips advices and et
Hi, -I wrote some codes for these modules(serial receiver & transmitter). -Both were synthesized and implemented on Spartan-3 and they worked correctly. -I want to use them as components in another module so i need the codes to be more modular than now. This is the Receiver : entity Receiver is Port ( Clk :
Following simple question: When I add a SPI 3-wire serial interface in QSYS I can set several parameters like: Type, clock speed, data width etc.. So why do I need those parameters when I setup the SPI interface directly in vhdl? In other words, are those parameters only valid when I this interface with a NIOS? Thanks!
I want to implement rs232 receiver in vhdl with FPGA Altera DE1. I have try to write some code but I know that is not good, my main problem is that I dont know how to get an indictaion that new data(serial data) is actually what I did is to move each bit of the serial data to the out parallel data (8 bits) every rising edge of the main
i use ISE for vhdl code, type matrix5x5_8 is array(4 downto 0,4 downto 0) of std_logic_vector(7 downto 0); thanks very much, i must use uart(its for serial input) to receive data, can u help me for it.
Hello, I want to describe in vhdl a generator parallel 4 bits to serial 1 bit. Indeed, at each clock edge (250 kHz), we take only one bit starting with the least significant bit (LSB). Example: Input = "0101" (over 4 bits) So at first clock edge, output = '1' (LSB) Second clock edge, output = '0' Third clock edge, output = '1' Fourth clock
hi I was trying to make a ramp voltage using spi dac8311 which will be interfaced with the altera de1 soc board through GPIO bus. thee clock needs to be divided down to 5 mhz for DAC OPERATION and ramp voltagE should be between 0 and 3 V. In my code down, i wan to increase the value by 3 every time the register is updated and then pass this val
Hello K-J, this is the vhdl Code. The main problem is that the counter CountSTATUS is always '0'. Why? Thanks! library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity ANELL_LEDS_v1 is port (clk, rst: in std_logic; -- I/O definitions DataOut : out std_logic);
Hellow Everyone, could any one post me spi slave code in vhdl by using cpol and cpha? I have written one code but my slave code is able to receive data from master but the miso doesn't have any data. The slave receiving data also not perfect some times some random data is receiving like with bit shifting. Following is my slave code --------
Hello Everyone, I am working on some codes for the serial-to-parallel fact I need to convert 6 serial values ( from 6 sensors which have already been converted to digital form) to parallel form which will be later fed to a comparator... I wrote some codes but I am encountering some errors...I would highly appreciate some help...
There is still allot of functionality that i need to add to my code like the ECC etc. But initially I want to be able to read, write a page and to get a structured addressing system going then if I know its working ill build the rest from there. I should be finished later today or tomorrow with the basic structure of
Hello, I am working on a project related to implementation on FPGA using vhdl coding. At first i do not know that real data type will not work for synthesis. Now I need to perform a function like Y=(a1*x1+a2*x1+.........+a8*x8) where (a1,a2....) and (x1,x2,....) are real numbers(with decimal point) using xilinks ise tool and have to implement it
I need a simple spi interface to be implemented in a cpld to enable communication with a tracking resolver (e.g. ad2s 12-series, read serial data as speed, angular position and writing resolver settings). Does anyone have a vhdl file that gives a good starting point? Also a model for a resolver in vhdl that could be used in a TB (test) (...)
The code below reads 40 bits of data sent in serial from a DHT-11 temperature/humidity sensor and stores the data in a 5 byte array of RAM. The code is: // Return values: // DHTLIB_OK 0 => OK // DHTLIB_ERROR_CHECKSUM -1 => Checksum error // DHTLIB_ERROR_TIMEOUT -2 => Timeout int read(int pin) { uint8_
hello, I want to make RS232 serial interface of fpga with pc. i need a vhdl code for this. also i want to know how to assign the pins in the fpga for this? I am using xillinx spartan 3 kit. thank you. Hi priteshkukadia, here is the sample reference code for serial communication with fpga.
Hi I want to implement parallel crc calculation for modbus(rtu protocol) in vhdl (not by using serial process or loops). Free CRC tools like output logic or easics do not give correct logic for modbus as they use CRC-16ccit.Even with modbus polynomial they give incorrect output. Lookup table can be used for parallel implementation however it
I am working on writing vhdl code for serial multiplier but am stuck on port map. I have uploaded an image for you to see what I am dealing with : Here is my code so far: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_STD.all; entity bitserial is Port