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6 Threads found on Vhdl Shift Reg
Hi all, i searched to see if there were other threads that could help me solve this, but found nothing useful enough.. i'm new at vhdl, and i have a problem- i'm supposed to create a generic shift register that also samples the the mid-values (as oppose to just the last output) my problem is that for some reason (i'm probably doing (...)
I got a text paper today, there are 3 questions below that I don't know how to answer them. Can somebody help out? Huge thxs. 1. Design a program with Verilog or vhdl which can detect a series of bits (such as 1010) in a long serial stream. 2. Supposing that you are going to design an electric system. Please describe the design flow from sche
One very easy method is to use an LFSR. That's a shift register with an XNOR feedback gate and a one-bit output. Here is an 18-bit LFSR in Verilog (probably easy translate to vhdl): module top (clk, noisebit); input clk; reg lfsr=0; output noisebit; assign noisebit = lfsr; (...)
Not sure exactly if I understand your question. Do you wish to constantly feed the output to something? If so, you can send the output wherever you wish, after a clock edge, the shifted data is present all the time at register ouput. You can either send it to another flip-flop, or you can do continuous assignment so that the output enter into
Try . There You cam find exampoles of E1/T1 framer in vhdl. May be it'll help You.
I wrot a vhdl design and I need to delay a signal for certain number of clocks, I write code for the shift register and I used its output. when I synthesuzed it I get a warining that the signal (declar the shift register) is not used and optimized. How can I force the synthesizer to keep this signal as it is.