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213 Threads found on Vhdl Statement
Sorry - misread code originally. Check that the RTL diagram actually has the hardware you think. I know quartus has had bugs in the past with this type of code. - - - Updated - - - try this code instead, it is functionally identical: process(D_Add) begin LdBuf <= (others => '0');
Correct. The "to_unsigned" is necessary because "100" is an integer and because vhdl is a strongly typed language a comparison between an integer and an Unsigned is illegal. Comparison between unsigned and integer is legal as "=" is defined in numeric_std. But comparison between std_logic_vector and integer is not def
I have a question for the following statement: I was checking logical equivalence between verilog and .lib using cadence conformal As I know LEC is done between similar files, vhdl vs vhdl or Verilog vs Verilog. (When you get bronze netlist is not the final one, still designer may expect changes in RTL. Silver more or less R
The statement slow_clk'event and slow_clk = '1' is used to detect a going to logic 1 edge on slow_clk. Good vhdl coders know this is deprecated in favor of the function rising_edge(slow_clk). The 'event version suffers from it triggering on anything -> '1', so 'X'->'1', 'Z'->'1', etc will be seen as a clock edge. The enable is an ext
Hello everyone. I want to use some data from external file in my testbench. Loading data from file: ------------------------------------------ --LOADING DATA FROM FILE----------- ------------------------------------------ type signal_storage is array (integer range <>)of std_logic_vector (data_width-1 downto 0); signal mem : signa
Signals are updated at end of a process and thus signal assignments can be written in any order; variables are updated immediately and this their processing is done sequentially. signals cannot be delcared in a process before the begin statement, they can be declared before begin statement of architecture. In constr
I'd have to check the synthesis results, but I think the char : char + 1; might result in an implementation where the select to the multiplexer is a register (char) followed by an add by 1 before being used to select the mux output. Not an optimal circuit for performance, this is a direct result of using a variable as it is evaluated immedia
I am using ise14.1 vhdl I have a record type t_ChargeProperties is record Charge : t_Charge; --10 Time : t_Time;--10 Row : t_Row;--6 Pad : t_Pad;--8 --Gain : t_Gain;--13 --Branch : t_Branch;--1 FLPad : std_logic;--1 end record; and types type t_ChargeProperties_stream is array ( 0 to
Hello, I'm a beginner at vhdl. I couldn't find an answer to this online: What is the difference between using the for generate and for loop when performing signal assignments? EX: for i in 0 to 7 generate a(i) <= b(i); end generate; for i in 0 to 7 loop a(i) <= b(i); end loop; Thank you!
I must implement in vhdl a neural network capable of recognizing these characters: left arrow, right arrow, up arrow and down arrow. I need to use as a template matrix 7 * 5. I also to be and code in Matlab for it.
You're p1 process looks like you are trying to write software (and the fact that you called the entity main). All of the statements are run in parallel. I'm not even sure the while loops will work correctly as a delay, but as I never write code like that I could be wrong and they do work as you expect. I would instead write
Google will u need it in vhdl only or verilog is also ok for you ?
"wait" statement cannot be synthesis ... Yes it can, but its not the recommended style. The following will synthesise to a register: process begin wait until rising_edge(clk) q <= d; end process;
sorry :(.I didnt put them because the question would be too long,and nobody read it. LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.numeric_std.all; use std.textio.all; use ieee.std_logic_textio.all; ENTITY x1_tb IS END x1_tb; ARCHITECTURE behavior OF x1_tb IS -- Component Declaration for the Unit
String in vhdl is declared as a character array. Thus, in my case I have declared a string that can contain the largest string assigned to it in a select case construct: So I have: variable instr_str : string (1 to 4); and then assigning value to it in case statement. case instr(5 downto 0) is when alu_add => instr_str := "add"; when alu_
I have a memory initialized from text file ,the contents of the text file is binary data I used LFSR to store this data in my memory with random address then i need to make some operations on this data then back it to the memory but the operations not performed and i cant know the error because during compiling no errors appear this is the c
Your design may work, but it is better to following the "the golden rules of vhdl style coding". Only sequential statements are allowed inside a process statement. An architecture statement part is comprised of zero or more concurrent statements. Better to keep the assignment of signals outside the (...)
--------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:30:01 05/25/2015 -- Design Name: -- Module Name: count - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- R
please someone explain me in simple wprds that when to use process in vhdl , and which signals are to be added in the sensitivity list .i have read some tutorial but unable to understand clearly.
I am getting this error ERROR:Xst:841 - "H:/Carry increment/carryincrement/carryincrement.vhd" line 98: Bad condition in wait statement, or only one clock per process. 117283