310 Threads found on edaboard.com: Vhdl Testbench
I am trying to set up a vhdl testbench for my project in Vivado. I want to make a simulation from the top level perspective and not just simulating an IP core. Vivado already added the HDL wrapper for the simulation, but I'd rather use my own testbench instead of the wrapper.
I started creating a new file, copied and (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-01-2017 10:28 :: MOd24 :: Replies: 3 :: Views: 891
I have simulated the following code using ModelSim.
entity fifo_SCnt is
RAMsize: integer := 256;
DataWidth: integer := 8
clk: in std_logic;
rst: in std_logic;
data_in: in std_logi
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-25-2017 15:07 :: muhammad_ali :: Replies: 4 :: Views: 523
Upto Line nos 108 is visible.
There are numerous eg of vhdl file read floating around. Study one of them and compare it with your code.
file file_pointer : text;
--Open the file write.txt from the specified location for writing(WRITE_MODE).
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-20-2017 21:02 :: dpaul :: Replies: 5 :: Views: 598
Hello everyone. I want to use some data from external file in my testbench.
Loading data from file:
--LOADING DATA FROM FILE-----------
type signal_storage is array (integer range <>)of std_logic_vector (data_width-1 downto 0);
signal mem : signa
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-27-2016 19:50 :: ustinoff :: Replies: 1 :: Views: 978
First off, if you're new to vhdl, I suggest you stay away from variables entirely. There is nothing you can do with variables that you cannot do with a signal. Signals will give you behaviour you expect, whereas variables do have some gotchas with them.
Without a testbench, it can be difficult to see whats going wrong. With simulation you can ea
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-25-2016 09:50 :: TrickyDicky :: Replies: 31 :: Views: 2663
Aren't vhdl or System Verilog enumeration types decoded by your simulator?
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-18-2016 12:36 :: FvM :: Replies: 6 :: Views: 649
Many years ago some one told me that it is better to have a verilog/SV testbench for GLS rather than vhdl.
Can some one please explain me why ?
ASIC Design Methodologies and Tools (Digital) :: 09-06-2016 12:32 :: sythe :: Replies: 1 :: Views: 528
As mentioned above writing a test-bench in Verilog/vhdl is the best way to do it.
Another crude method would be to force the desired input signals and see the output. This processes is highly discouraged!
Software Problems, Hints and Reviews :: 08-29-2016 14:22 :: dpaul :: Replies: 2 :: Views: 678
p_fmcw : process(reset_n_i, clk_128m_i)
if (reset_n_i = '0') then
temp_s <= 0;
cnt_s <= '0';
elsif (clk_128m_i'event and clk_128m_i = '1') then
if (enable_i = '1' and fmcw_trig_i = '1') then
if (temp_s = 0) then
temp_s <= temp_s + to_integer(unsigned(fstep_
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-29-2016 07:07 :: Vijay Vinay :: Replies: 0 :: Views: 44
How about using a counter with a 10 Hz clock (1 ms period) or use whatever system clock you have, e.g. 100 MHz clock and create a counter that counts from 0-9,999,999-0 and increment a second counter when you reach 9,999,999 (or at 0,000,001 for a starting increment).
Instead of giving the simulator lots of work to do
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-25-2016 15:38 :: TrickyDicky :: Replies: 7 :: Views: 778
No. I am pretty new to vhdl. I am still learning my way around the Xilinx ISE and vhdl as such. I am in the process. In the mean time if someone could comment on the query it ll be helpful
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-15-2016 20:20 :: arve9066 :: Replies: 4 :: Views: 682
for a testbench:
wait for 1s;
wait for 1s;
-- do something else
Note that this code is ONLY for testbenches. It cannot be used on a chip because circuits have no understanding of time. In a real circuit you would have to build a counter and enable.
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-04-2016 11:59 :: TrickyDicky :: Replies: 1 :: Views: 338
Without seeing the netlist and/or the simulation testbench we can only guess.
You mention in your first post that you did a behavioral simulation of the vhdl. Are you using the same testbench for both the behavioral and netlist simulation?
- - - Updated - - -
Also are you sure that there isn't a GSR i
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-31-2016 22:52 :: ads-ee :: Replies: 3 :: Views: 701
ENTITY dwt IS
clk : IN STD_LOGIC;
vid_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Pixels from main memory
hor_sync: IN STD_LOGIC;
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-29-2016 06:32 :: 214 :: Replies: 5 :: Views: 621
I am trying to write a code in vhdl with a given time period of clock in testbench .When i execute it i get proper output , but if i modify the code slightly i.e including more functions (more operations) then although am not changing anything in the test bench , but still i the clock in the test bench waveform appears to have g
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-13-2016 06:29 :: xtcx :: Replies: 7 :: Views: 773
Could you pls helm me with cordic vhdl testbench for this code
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-12-2016 14:21 :: Kosyas41 :: Replies: 0 :: Views: 1
Can any one help me declare a variable array. in avhdl for a papilio one
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-14-2016 08:41 :: fisat :: Replies: 1 :: Views: 467
All numbers that calculated are pseudorandom. Even if you feed them with the system time, the resulting sequence is psuedorandom, based on a given distribution. Getting truly random input in a vhdl testbench would be very difficult, as it would hard to hook into a RNG system function (which usually uses something like thermal noise to create a rand
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-18-2016 11:26 :: TrickyDicky :: Replies: 4 :: Views: 1599
How do we create a testbench in vhdl AMS? The platform I have used is Hamster vhdl
PCB Routing Schematic Layout software and Simulation :: 12-29-2015 15:26 :: Arushi Jain :: Replies: 0 :: Views: 440
I am engineering student i want write a code in vhdl go get the simulations as per the picture attached and tried doing that but not getting please help me with the code.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-26-2015 09:57 :: Anupama shetter :: Replies: 1 :: Views: 524