Search Engine www.edaboard.com

Vhdl Viterbi

Add Question

20 Threads found on edaboard.com: Vhdl Viterbi
Hey people, I am working on viterbi decoding in vhdl. I am using altera quartusII 6.0. I am posting the code and the problem, please help me rectifyy utlibrary ieee; library work; use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; use work.data_packages.all; entity viterbi_decode is port (path_calc: buffer
Hi all, I also working in viterbi decoder using fpga. Anyone have the verilog/vhdl code ? Could u all forward it to me? pineballerz@yahoo.com Your help is much appreciated. Thanks. -azlan-
Hi Kindly send the project report of the viterbi decoder, atleast the code Thanks for the answers
can anyone help me by letting me know where i will get the vhdl code for list-of-two viterbi decoder?
can i have help for vhdl coding for acs in viterbi decoder
it is very easy way because matlab include viterbi decoder and this is away to convert it to vhdl just write in matlab command window >>demos and see demos about simulik=>hdl coder=>communication=>viterbi decoder use matlab 2008a or higher
hello every one I am doing viterbi decoder with vhdl k=3 r=1/2 I have done the encoder part of it and I am middle of deocder I have problem for codding the hamming distance should I do it in trellis codes or branchmertic code can any ine help me please. thank you in advance
could any one help to write my code in vhdl for viterbi decoder 1/2 rate with constraint length 3 I did some coding for a start but I'm not sure is it correct or not LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; entity generatorcode is port( clk : in std_logic; reset :
you can find the code in the and material can be found in digital communication book by bernard sklar therez another book which i dont remmember exactly but itz title is something like digital design with vhdl where he describes it as an example of FSM haneet
Hi every body ,i am implementing a Turbo decoder sova (soft output viterbi algorithm) on vhdl languge 2 decodeur sova code rate = 1/3 Matrice generator g= state
Hi every body i am implimenting turbo code in FPGA ,the turbo decoder sova (soft output viterbi algorithm): 2 decodeur sova code rate = 1/3 code generator g==> k=3, n=2 state number 4 . I need some help,if you hv code source vhdl of turbo or some doc?? i will be greatful plz ,i really need your help
I have following requirements for the project please help me by sending the links for the following.... vhdl code for........... 512 point FFT IDCT, LOGARITHM, HMM and viterbi algorithm
hey can anyone send the vhdl code for (3,1,4) convolutional code viterbi decoder.. or atleast the traceback unit of the decoder... urgent pls help ! thanks in advance :)
hi all I have a question could you please tell me what is butterfly I am now involved in implementing a viterbi decoder using vhdl I found a model for the ACS unit using smaller units called "butterfly" I googled it but no use thanks
hi every body i am having a problem while doin timing simulation of my vhdl code of viterbi decoder. errors are ** Error: new_testbnch.vhd(57): Signal "code_rate" is type ieee.numeric_std.unsigned; expecting type ieee.std_logic_1164.std_logic. # ** Error: new_testbnch.vhd(57): Signal "data_i" is type ieee.numeric_std.unsigned; expecting type
hello; i am a student and i need in my project the vhdl code of the soft output viterbi decoder ,please help me as soon as possible. it would be a valuble suggestion from you. thanks and regards. my email is
guys, does any one have any idea about viterbi decoding with turbo codes in vhdl
Hi Does anybody have free Reed-Solomon libaries and viterbi libaries for vhdl en C. I used the library from Phil Karn but there are errors in them. Paul. if I rember right you have lot of working reed solomo-codes in linux kernel to handle QIC-tape drivers via floppy drive interface (QIC-20, QIC-40, QIC-100, IOMEGA
I think you can find some Verilog or vhdl example of viterbi decoder on ipcore website.
Hi I need source code for high performance viterbi decoder(50Mb input) in vhdl language. Can anyone help me? Thanks in advance. :?: