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39 Threads found on Virtuoso Select
Hi all, I have a problem in layout design. I have a capacitor in my schematic and when I start doing layout I do generate all from source. I want to do "flatten" and modify the layout of that capacitor. I do it and make new cell and save it. Now, the problem is when I do this, layout and schematic does not match and i
Go to virtuoso window, maybe there is a option of exporting schematic under file menu. select CDL.
Hi, I am new to Cadence I created a basic CMOS inverter using Layout. Now before extracting I was told to Merge the layout. When I click Edit > Basic > Merge I see that there is an error popping up. It says that merge command was unsuccesful because all objects are in different shape. How do I resolve this ? PFA for the e
Dear all, Recently, I've found that I cannot do a simultaneous selection in virtuoso Layout. For example, 120141 I cannot select the two metal traces (A & B) at the same time. I'm highly suspicious of the Option Setting, which has not been properly set. BTW, my virtuoso Virsion is IC615 Can anybody give me
My aim is to make an image out of an schematic in cadence virtuoso without all of the displayed properties, ie I'd like to have only wires and compoents on the image. Is there away to hide all properties and than to show them again without disabling the properties manually for each component?
Hi everyone, My issue is about a DC simulation. When this one is finished, and I wanted annotate the DC operating points on the schematic, They are not displayed for all components. For example, I've 2 dc sources, but the DC operating point is displayed only for one of them. I save all the points (Output -> Save all -> check boxes on "al
Hi, I am designing a datapath circuit, but I am having trouble with cadence software virtuoso & My circuit can't netlist, but sometimes it does netlist after a few hours, even if nothing got changed in between. Sometimes i select 'escape names', and it netlists, other times it doesn't even if i select it or delete the run folder. (...)
Hi, I am using virtuoso 6.1.6 and have encountered an issue. I usually am able to select a group of pins (pin layers) and copy them between layout windows. However now some pins will copy and some will not. All were made individually so do not hold any history in them. I've tried placing a cell of pins and flattening it (done with both pre
hai friends can any one help me in this regard steps to calculate nmos and pmos threshold voltage using Cadence- virtuoso- ADE L thanks in advance
Hi , i am new user in cadence , i want to ask how to copy instance in virtuoso schematic XL? Thanks : )
HI, I want to export a transistor model from virtuoso library to ADS. I need your help thank you
I want to overwrite process rule like spacing between two metal in cadence module generator utility. I am able to do the same in cadence virtuoso layout editor by using process rule editor by defining new rule and selecting this new rule in automatic router. but, with module generator utility I have no option to select the used defined (...)
I have made a layout structure consisting of 20 to 30 smaller components plus additional metal paths and pins. This was made as a revision to an older design and after a lot of changes and therefore the origin is not at 0,0. QUESTION : How do I move all the components w.r.t each other to the Origin 0,0 ? Meaning I don?t want to ske
Without having currently access to virtuoso, I just remember the following -- don't know if it really works like this: 1. select all these terminals 2. Hit "q" (query) 3. Change the "only current" field into "all selected" 4. Click "Display Pin Name" to display pin names.
sir, i would like to do project in cadence but i have no one to guide me in right path to select a project please suggest me cadence virtuoso related projects pls kindly help me sir
Hi, i am saving the gds frm encounter via streamOut command and then streaming in in the virtuoso. When i am running the lvs on the exported gds, It shows ports mismatch problem. Actually encounter is making the labels in M1 drawing instead of M1 pin layer when i am reading in the virtuoso. When i am manually changing the
Hi, The techfile from my foundry is *.asc. However, Cadence version cannot see *.asc files. It can only see file. How can I load *.asc techfile in this version? Also, I was using an older version of cadence virtuoso and it can see *.asc files whenever I select the techfile. Its just wierd why on this latest version, it can only s
Does anyone know how I can select to display the cell's parameters WITHOUT running a simulation first in virtuoso schematic? I place the pfets and nfets and I have to click "properties" to check there parameters whereas if I run a simulation, I can do an "annotate" and everything is displayed. Does anyone knows a more direct approach? Th
hi how can I copy and paste a schematic (a circuit containing some objects) from one virtuoso page to a new design page in virtuoso? I am linux and CTR+C/V doesn't work. I read a same message in edaboard but it is about text copying not circuit copying. I select the circuit and then press the C key but I could paste it in the same window (...)
I am currently doing an assignment using virtuoso Schematic Editor using Spectre analysis and analog.lib - perform dc sweep analysis for a current mirror. I can't plot the graph for the current flowing through the transistors. Whenever I click Results > Direct Plot > Main Form in analog environment, it keeps showing "There is currently no analys