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6 Threads found on Virtuoso Speed
Dear All, I am running some small-size transient simulations using Spectre simulator in virtuoso. that includes some veriloga blocks and a small transistor level one. Although, through the ADE window save options, I disable all saving of nodes/currents/variables I am still getting a huge and fastly increasing file size for the file "tran.tra
@psrkforuvlsi, This facility is there in virtuoso-XL tool. Try it.
IC Station and virtuoso? Which is better?? In my opinion, i see that Mentor IC Station provides many helpful and speeding-up features specially in analog layout and matching.. I hope that experienced ppl, kindly share their valuable experience to compare between them both, either in features, design speed, etc. Also, can IC station be (...)
hspice simulation can be executed directly in virtuoso envirment. you can also use hspice by input netlist, and it's simulation control option is more powerful than spectre
Our company have made a comparison of access speed to the virtuoso Layout on a Sun Blade W2k XWin32 W2k XManager W2k Exceed 9.0 W2k RealVNC Linux@PC rlogin & Display Redirection Solaris@SUN rlogin & Display Redirection If the remote was a W2k-PC Exceed was the fastest. RealVNC the slowest. Exceed is already faster than a Linux client. Bu
hi , we are encountring while using the gpdk PDK from cadence for eductaional purpose. The models for 0.18u are defined under gpdk.scs ,nmos1.scs, pmos1.scs . err1 : while placing a pmos ,nmos symbol in the window , in properties it shows the model name as PMOS1,NMOS1 which are not changable. While netlist and run --> in the input.