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76 Threads found on edaboard.com: Why Setup Time
Hi folks, I have seen few zero cycle ( set_multicycle_path 0) setup paths in design. Can you explain why there is a need of having 0 cycle setup path? what is a advantage of the same? How do we check hold violations for these kind of paths? These paths are violating setup time. How can fix this issue (...)
If the data at input of Master latch changes and at that instant the clock of master latch had not gone into inactive level, then we might enter into metastability. why? Can you explain physically why a metastability happens?
I am simulating in terahertz (THz) range which source resistance is high (>10 Kohms), I want to obtain S-parameters and input impedance but i saw that in some frequencies the amount of S-parameters are larger than 0 dB and real part of input impedance is also negative. i think they are not reasonable, can anyone explain what is wrong in my simul
why? The PWM controller can be either used with feedback to regulate a voltage or with fixed duty cycle but not both at the same time.
Hi all, why static timing analysis is not efficient for asynchronous designs..please explain . Thanks
1. why not inspect the include file to answer the question yourself? 2. The result registers receive the AD value for the currently selected channel. If you mux between multiple channels, you must provide sufficient wait time for filter setup. 3. I don't see that OSR changes the ADC scaling. You should consult the description in the (...)
Hi All, i've a confusion why worst case report is considered as the Max delay violation(setup violation) and Best case report as Min delay(hold violations). And why we always calculate the hold violations at the launching flop. thanks in advance, Arjun
am i still getting mixed up here? if so that explains why this still won't work. thanks for the help :) iv got this code working on a PIC 16f877a so why wont it on the PIC 16F1937 /* 3x4 Keypad with PIC 16F1937 in MikroC */ #include"7_seg_Lib.h" const char Column={0x01,0x02,0x04,0x08}; void main() { char Keypad=255,x=0;
why does a plug in bench DVM meter short out when measuring VCC and VDD at the same time? VCC is -30volts and VDD is -30 volts The Bench DVM meter shorts out the burns the circuit board, but why? How do you prevent this from happening? - - - Updated - - - Corrected sorry VCC is +30volts and
why don't you just use a polyfuse with the correct current rating for the lamp? When the short is removed it will reset by itself.
Hi All, When I do hold time analysis after P&R using Primetime, I find a phenomenon that there are usually more hold time violations in best corner than in worst corner for the same design. I don't understand why this phenomenon exists. Let's assume the clock slew of the design is 0 to simplify the topic to be (...)
Hi, I do a report_timing in dc_shell and I get a huge library setup time of -123.44ns You can see the last part of the timing report: Can you guess why a 40nm cell (FF) should have such a huge library setup time? clock period is 2.5ns Thanks Alex node_1/index_reg/D (SDFQND2BWP) (...)
Hi, In following timing report (generated by "report_timing -nets -capacitance -nworst 10"), output (ZN) of U65427 has 160.79ns delay. You can see this instance has one load (fanout). I need to find the reason for this big delay and resolve it. Also why library setup time is so huge? Design size is 5 million gate.(160ns seems to be (...)
Hello sir. I am reading about lockup latches. Sir how exactly lockup cell removes the hold violation? And sir why we do check setup analysis in next clock and not at the same clock? If first clock for destination clock laging the source clock and during that time if data can settle then what will be happen? And why we are (...)
please explain what is setup and hold time? what are its causes? and why it is so important??
Hi all, 1. What is the meaning of setup time for SAVE pin ( asynch pin ) of a retention register wrt CP pin. 2. If SAVE pin is active high, then why only fall_constraint is considered for setup_rising ( CP rising edge ) in .LIB file ? Regards & Thanks, Nitin
I wonder how the fanout contribute to the setup time violation. Please advise.
setup time = Max Signal Delay - Minimum Clock Delay why we reduce Minimum Clock Delay if we dnt do that even our design will be more robust. So what is the reason of reducing Minimum Clock Delay from Max Signal Delay..
why we reduce Minimum clock delay in setup time formula: setup time, Tset = Maximum Signal delay ? Minimum Clock Delay Because if we do not reduce the Minimum clock delay our design will be more roboust. ??
why Hold time does not depend on frequency but setup time does?