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67 Threads found on edaboard.com: Width Verilog
Hi I disgned 128b/132b encoder and decoder block in verilog code but my data width is 8 bit and my encoder' s input in 128 bit so how can I communicate my data bus with encoder?how can this encoder get 16 8 bit symbol?
I am very new to functions, I have a parameter to specify the input freq(mhz). Would this return a value I could use to specify a vector width? function int _ms_unit_width; int freq_mhz = (int_input_freq_mhz/1000); _ms_unit_width = ($clog2(freq_mhz)+1); endfunction
Can you help me understanding this my_ByteSel = {8?d3, 8?d3} width = 8 my_pointer (value) `width * (value) +: `width Wire my_counter; this is what I would like to understand --> my_counter(my_ByteSel) assume that value will take  0 and 1 ? only two values. Thanks..
Hi, I am having a memory (depth = 64, width = parameter) to be read fully and put it in a 1-D array (width = 64*memory data width). Only 1 row can be read at a time. This is the verilog code I have written parameter MEM_DATA_width = 32; localparam DATA_width_O = (...)
Hi All, I am using verilog A model ofTFET from Penn State University which is given below. `include "constants.vams" `include "disciplines.vams" module NTFET(d,g,s); inout d,g,s; electrical g,d,s; real Ids, Cgs, Cgd, Qs, Qd,Qg; parameter real W=1; //Device width analog begin Ids=$table_model(V(d,s), (V(g,s)), "IdVg-NTFE
verilog requires that slices of bit vectors have constant width. Even though you could prove the range of your simple case has a constant width of 10, verilog does not allow that syntax. Use the +: range construct. See
For a signal whose word-length is a GENERIC, how to set all its bits to 1 in verilog? Using '1 is not supported in some synthesis tool because it's a systemverilog feature... Thanks You mean a parameter (Generic is VHDL). assign some_signal = {width_paramter{1'b1}};
You have to instantiate the alu module inside the ralu module if you want to have the op1, op2, func, and out to connect to anything in ralu. Right now you have two separate modules with no connections between them. You should fix the width of func, it's defined as 4-bit but should only be 3-bits. Add a default to the
I have a signal with 10 bit width. I want to assign do an operation while this 10 bit signal changes. Can anybody please let me know the synthesizable construct to indicate that whenver this signal 9:0 width changes , an operation can be done? Let the signal name be is high_volt. Whenever high_volt changes I need to do an addition of two o
I have an sram memory . it's data width , address bus width and depth all are sram depth is d and the address bus width must be log2(d) and represented by c parameter . I import the math function library by several methodes in my code but neither of them worked and there were errors. I don't know how to write the width of (...)
Hi all, How we can use the parameter as bit width in verilog for a CONSTANT value representation. For example : parameter VAL = 11; always @ ( posedge CLK or negedge RESETn ) begin if ( !RESETn ) begin count <= {VAL{1'b0}}; end else begin if ( count == 11'h5FF[/C
//RTL version module shiftReg( clk, rst, load, // enable load pIn bus contents into the register sen, // shift enable pin, sout // serial out ); parameter width = 4; parameter hi = 1'b1, lo = 1'b0; input clk, rst; input load; input sen; input pin; output sout; reg sreg; assign sout = sreg[
Hi, this is range definition. Previously defined parameter NUM_CLK_DOMAIN equals to width of VALID_CLK_DOMAIN parameter. If range is not defined, it would be 32 bits. {NUM_CLK_DOMAIN{1'b1}} here replication of concatenation is used. Let's say NUM_CLK_DOMAIN is 8, then VALID_CLK_DOMAIN parameter will be 8 bits wide, and will g
Form system verilog LRM 3.1a, Systemverilog adds the ability to specify unsized literal single bit values with a preceding apostrophe ( ? ), but without the base specifier. All bits of the unsized value are set to the value of the specified bit. In a self-determined context these literals have a width of 1 bit, and the value is treated (...)
Hi, I have the following system verilog code to be compiled in VCS. module (....); ..... ...... parameter width = 8; parameter = {8'h00, 8'hff, 8'h24} ; .... .. endmodule How can i parameterise the size of literals inside the concatenation? so that even if width changes i need not bother about changing the size m
Hello every one. I have same problem about below tx code. Here is a verilog uart transmit code. Here I can send only one character to computer via rs232. In below code can send only 'X' char. I need to send word by word to computer. Please help. module TX (
I have frame width of 64 * 64 pixels. each pixel width is 8 bits. Help me in writing verilog code for the frame.
Hi! I think the most easy way to do so is to write your own preprocessing script to generate the code you want according to some input parameter (in your case the data width). Since the code you are going to generate is very simple you won't have problems in writing a simple script. Then, invoke the script along the flow before going to synthesis.
Hi, If there are 3 single pulse signals, one of which (1st) follow 2nd signal with a delay 10ns, how to compare the other one(3rd) width with the delay value? If 3rd width equals that delay value, indicate it. Thanks.
have you checked whether A and Y is 1 bit width or 3 bit width?