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56 Threads found on Xilinx Adc
I am assuming that xilinx FPGA is the SPI master and the SPI IP is the slave for it. Then again for the adc interfacing, the SPI IP is the master and the adc is its slave. I can only provide some generic debug methods. Can you poll the status regs of the SPI IP from the FPGA master, i.e. do a read? Can you write something to the SPI IP from (...)
need help regarding interfacing adc 0808 with xilinx spartan 3E FPGA Hello guys, I am trying to interface adc 0808 or adc 0804 with papilio one.can anyone please tell me how to do verilog or VHDL program of this?. please help. thank you for your time and help
Don't know of any CPLDs with adcs - but there're a few FPGAs - most notably: the Fusion and Smart Fusion series from Actel and some devices from xilinx:
Problem: I have data sampled in an adc at 337.5 MHz(actually it is sampled at 1335 MHz,but for sake of DDR3RAM i am slowing down the rate at which data comes out,using 1:2 demux provided within adc) which needs to be written to a DDR3 RAM via a Virtex 7 fpga.(I am using xilinx Vivado Design Suite) My progress: To writ
So it is always advisable to use one external clock and design everything using that clock as a base clock and vary the frequencies as per required through well calculated pulses ( enables ) .I would certainly advise doing this in FPGAs. The reason is there are limited resources to get onto clock buffers in an FPGA fr
First of all, you'll either need an FPGA with a built-in Analog-to-Digital converter (like a xilinx Kintex, for example), or you'll need an external device. Pressure and temperature and such are relatively slow signals, so you won't need a very fast adc for those, but voice will require a faster device. You don't say anything about resolution: 8
hello, i need a vhdl code for fifo memory to store binary values from a high speed 8 bit resolution adc. can help me give the code and the ucf file for implementing it on spartan 6 sp605( fpga kit).?? thank you you can automatically generate it with xilinx core generator (coregen) you can find it under :
hello, can any one suggest me with a simplified vhdl code for interfacing spartan 6(sp605) with an ic adc 0804? adc 0804 data sheet. spa605 thank you. all you
Hi Could any one introduce an evaluation board containing spartan 3 fpga,2 analog to digital converter (minimum: 12 bit/4 Msps) and gigabit ethernet connection? I have already found some boards and kits in xilinx site which have some of these features but not all of them. If you know any similar products from other suppliers please tell me.
i m doing my project for video filtering using xilinx virtex 5 FPGA kit for real time videos i want to interface camera with the kit for real time implementation. can anyone help me about which digital camera will be better to use or can i use usb camera for interfacing. can you plz help me about any research paper or something like this for ca
PCB design: Cadence Allegro 15.2 / 15.7 / 16.2 / 16.5 Schematic design: FPGA, DSP, MCU, etc. adc / DAC high-speed interfaces Hardware design using xilinx and Altera FPGAs. e-mail:
Check this I think you misunderstood the OPs question, which wasn't about Altera or I/O delay. xilinx has an element called IODELAY, which allows for inserting a del
From altera you want the cyclone series. They have plenty of onboard ram and embedded multipliers for your FFT. xilinx would be the spartan or artix series.
Regarding FFT & IFFT CORE - xilinx User Community Forums Sir I am trying to use FFT 5.0 core in xilinx10.1 as follows for 50 hz SinWAVE(THROUGH adc)for noise removal 1. 64 Transform size 2. Radix-2 burst mode 3.I/p da
Sir I am trying to use FFT 5.0 core in xilinx as follows for 50 hz SinWAVE(THROUGH adc)for noise removal 1. 64 Transform size 2. Radix-2 burst mode 3.I/p data width 8 bit 4.Scaled 5. Natural order(without cylix prefix) I want to know what is the value of scale_sch. Further I want to use inverse FFT for the O/P fft i.e XK_REAL AND XK_IMA. a
I had used Avnet xilinx Virtex-4 MB Development Kit with P240 analog module about 2 years back. You will get cheaper boards with better specs now.
You could check out DDS Compiler for xilinx.
Hello people, I would like to use the adc in my FPGA kit described in this user guide, page 71: I would like to know. Must I use the amplifier? I want to configure it minimally if possible!! I don't want to amplify the signal! and what configuration should I use if I
I found this from a xilinx White paper "A synchronous RAM cannot perform read-modify-write operations in a single clock cycle, but the dual-port, synchronous block RAM in all xilinx? FPGAs can pipeline the write operation and achieve a throughput of one read-modify-write operation per clock cycle. To do so, the designer uses Port A as the read
No way. You cannot model a risistance in VHDL, especially for FPGA project. You may use VHDL-A but that cannot be used to FPGA, at least xilinx's FPGAs.