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169 Threads found on Xilinx Library
Maybe it is a trivial error somewhere, I can only guess! This is from a similar xilinx Answer Record: When you instantiate components from a xilinx or user library, be sure to match component names and pins exactly. Verilog is case-sensitive, and if the case of the module name in your instantiation does not match the case of the module declarat
hello all I want to simulate a simple data acquisition system in matlab simulink. I use xilinx fir compiler v6.0 and when i ran the simulation gave me this error: Error reported by S-function 'sysgen' in 'DAQ_simulation/FIR Compiler 5.0 ': An internal error occurred in the xilinx Blockset library. this is my system 131684[/ATTACH
Hi. I'm trying to implement with IPIF. Now I'm following problem is following 131022 AXI_LITE_IPIF_I does not resolved in th
I have installed xilinx ISe system generator. It has been configured for MATLAB. But when I open system generator, MATLAB is opening and in that when I open simulink, xilinx blockset is missing. Can anybody suggest how to configure xilinx blockset in simulink.
Looks like Altera does something different than xilinx. It appears you are also supposed to compile a .vo file along with your netlist. See here xilinx simply requires you add "-L simprims_ver" to the command.
I have a xilinx VHDL IP which I am compiling along with other Verilog and SV design files. I am compiling the VHDL design files first. Prior to compiling the VHDL design files, I have compiled the xilinx VHDL libs using the command: compxlib -s vcs -p /home/shared/Synopsys/I-2014.03-SP1/bin/ -arch spartan6 -dir (...)
My design has Verilog and VHDL modules along with xilinx primitives.There are no problems with the xilinx Verilog libs. I have also compiled all the xilinx VHDL libraries (a dir has been created with the compiled libs and I also have an error free log file. I had used the xilinx command COMPXLIB for compilation of the (...)
DIGGING UP THE OLD THREAD.... Hi dharag, were you able to find a solution to the problem? Actually I am facing a similar problem now, while integrating a VHDL xilinx IP in a Verilog top-level design and compiling with VCS. I have created a separate filelist and compiling whatever us under unisims ans unimacro. # VHDL unisim and unimacro
ERROR:HDLParsers:3014 - "C:/xilinx project/Sequencial_filter/Sequencial_filter.vhd" Line 28. library unit types is not available in library work. while compiling my VHDL code i'm getting this error, please help me.
Hi i want to implement , multiplication of 2 matrix. A*B=C . I want this for implementation on FPGA with xilinx , before all i have no error with the code (on MODELSIM) . but my output, get wrong answer , i don't where is my code wrong , so need help , plzzz :( here my code : library IEEE; --USE ieee.std_logic_1164.all;
1) Put a known signal in and see if you get the proper output. 2) It most certainly is synthesizable. 3) What do you mean "how to use chipscope"? Do you have a specific question, or are you asking for a tutorial instead of reading the manual? 4) A digilink cable, as far as I know, is for some kind of network connection. I have no idea how it app
I came across this library in vhdl use work.cpu_lib.all; How do i use this library? I typed it out but it didn't recognize it as a key word. I mean for regular libraries and key words the color of the text changes to blue right? But this one didn't. What should I do.
Hello, I want to translate schematic and pcb library from an Allegro designed board to Altium cause I need to use most of the components of this board and I don't want to redesign schematic symbols and footprints. Is there a way to do that? I interesting for xilinx Kintex 7 board kc705. Here are the files
ERROR:Xst:1547 - C:/xilinx/bin/fft1/fft1.vhd line 8: Signal of type real is not supported. Come on now, really? The message is pretty self explanatory. Main code: library IEEE; use IEEE.std_logic_1164.all; use IEEE.MATH_REAL.ALL; package fft_pkg is type complex is
You generally dont get VHDL output from synthesis - are you outputting some VHDL module for post map simulation? What version of XST is it? XST, especially older versions, are pretty poor. Did you use the xilinx version of the float compatibility library? I wouldnt use the float package anyway - there is no pipelining so performance will be terrib
i have done a program in xilinx(ripple carry adder in structural modeling). library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ripple is Port ( x : in STD_LOGIC_VECTOR (3 downto 0); y : in STD_LOGIC_VECTOR (3 downto 0); c : in STD_LOG
Try this and check if it works: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; ENTITY txbuffer IS POR
hello all, i tried to add packge and component in and function my top code is : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity top is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : out STD_LOGIC); end top; archi
use the xilinx floating point library blocks.
Do you want to generate the the sin/cos function or a lookup table? If you actually want to generate the function on-the-fly, use a CORDIC. xilinx has, I believe, a free IP module. I have no idea what that library is; it's certainly not a standard VHDL library that I'm aware of.

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