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15 Threads found on edaboard.com: Xilinx Loading
If it is a xilinx Chip, you can use the textio functions to set the initial contents of the ram.
Is there a problem in using ModelSim inside Vivado not recognizing the ELF file generated by xilinx SDK? I don't know for sure if there is some procedure to make ModelSim recognize that, please look into the related docs/specs. I have never come across this use case in my work. The ELF file is generally associated with the uB, and when you supply
Looks like Altera does something different than xilinx. It appears you are also supposed to compile a .vo file along with your netlist. See here xilinx simply requires you add "-L simprims_ver" to the command.
If you wsh to avoid that altogether, you can turn to flash based FPGAS. CPLDs (like the MAX and Coolrunner series from Altera and xilinx) are examples but there are more potent full fledged FPGAS available, notably from Actel/Microsemi. These are pretty much "up" as soon as you power them, often at a lower power budget too ;)
I am seeing a similar issue when loading my device driver for a custom peripheral. Used chipscope to inspect the bus signals and found the bus was signaling a DECERR so I thought this may have been the cause: But if it is I don't know how to fix the problem. If anyone has solved this issue pl
I'm working with a board that has a problem with parallel loading. It's A Spartan 3 FPGA with an XCF08P flash. The firmware loads without issues when serial configuration is set. However, it doesn't work with parllel loading. Any ideas ?
hi all, can anyone help me converting a xilinx system generator block model to a bit file for loading in an fpga?
Hi, I am simulatin my VHDL code in modelsim through xilinx ISE there are many cases that when I run simulation modelsim runs and stops at below stage!... I don't see what has caused this problem: # vsim -lib work -voptargs=\"+acc\" -t 100ps work.SDI_Ftest # loading std.standard # loading ieee.std_logic_1164(body) # (...)
I have been learning how to write VHDL using the book "FPGA prototyping by VHDL examples: xilinx Spartan-3 version" and I'm working through the FSMD design examples and loading testbench vectors from external files and writing the output data to text files to quickly view without having to check the waveforms. But in my output I was getting some
'Practical' in the sense what?? I have a simulink model with xilinx blocks, out of that i am generating bit stream file and loading it on hardware and running it. It works fine. If it can helps you in anyway then let me know, i will mail u. --- Ashwini
I have taken a xilinx CoreGen's FFT core and i tried to simulate in ModelSIM. After compilation and when i was loading my design i got an error "Failed to find 'glbl' in hierarchical name". How to clear this error. Thanks SUdhir
hi people, i have got a new xilinx virtex2p pro development system...i am not able to configure the board to JTAG USB my case the leds D14 and D19 are always glowing(MAP GOLDEN loading)...the problem persists even after rebooting and pressing the reset button.... ur valuable inputs are most welcome...
Maybe you haven't yet installed/configured the xilinx SmartModels for ModelSim. Refer to chapter "Using SmartModels" in your ISE "Synthesis and Simulation Design Guide".
hi. i have tried to simulate the post fit vhdl model in the modelsim, started from the xilinx-ISE for a Coolrunner2 CPLD, but it has an error: in the modelsim: ... # loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_roc(x_roc_v) # Error loading design # Error: Error loading design (...)
Hai, I would like to do hardware implementation for the algorithm (Pan and Tompkins for QRS detection) written in Matlab. I assumed that I can achieve it by loading the Matlab file into the Accelchip DSP synthesis tool and then exporting the output of Accelchip to the xilinx system generator.Finally, xilinx output is implemented in the (...)