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10 Threads found on edaboard.com: Xilinx Sdr
Hi there I am using a SPARTAN6 speed grade 3 and there is a high speed sdr SRAM In my board. I've used PLL to generate clock and out to SRAM. I set timing constraint but the max frequency I achieved is 125 MHz. If I increase the output clock of PLL to 150 MHz I have timing constraint error: "Slack in some nets is -3.447ns." How can I increase
Hi I want to drive a MT48LC sdr sdrAM with xilinx XC3S400. I couldn't find any core. Would someone please tell me how is scheduling of REFRESH? What is difference of REFRESH and PRECHARGE? When i need to perform a PRECHARGE? I would drive the sdrAM in the easiest manner. Just write some data and read it. Where should i (...)
I have been facing error problems in QPSK mapping for sdr, in xilinx ISE 12.3 :( I am attaching the screenshots here 685206852168522 Please help me to rectify these errors. Any help will be appreciated
Currently am working with SMT8246 sundance (WARP ) sdr kit V2. The xilinx system generator is Simulink. without using simulink hdl coder, how can i extract hdl code from simulink model?... How to dump simulink model into fpga board uding Diamond 3L software?
Here's another pointer: ComBlock > Home > Product List > COM-3011 Receiver / sdr This is a new receive-only sdr covering at least 20 MHz - 3 GHz. The development environment is (a) xilinx ISE for the FPGA and (b) Eclipse/gnu for the ARM Cortex M3 processor, if need
The spartan3 starter kit does not have any memory other than SRAM on it, if you want to connect any type of sdrAM to it, you have to make your own adapter board to connect to it. You can then make your own sdrAM controller or use the one generated by xilinx's MIG to access it. I am pretty sure you will have a lot of problems (...)
hi everyone, can anybody help me to design the MQAM receiver using sytem generator xilinx? i studied the example the 16QAM demodulator in the matlab..but it is too complicated since the application is for sdr. my design specification using veterbi decoder with awgn channel.. if someone can be so kind and experienced in system generator&s
hi every body i need a help in using system generator to convert from Simulink into VHDL (xilinx) for sdr project (soft ware defined radio receiver) that supports both AM and FM:!: thnx in advance
Where can I get a comprehensive list of high perfomance sdr Dev Kits? I searched in etc please help me
You can use IP cores that are developed for FPGA implementation. Many companies offer such IP cores for the wireless and telecommunication application domain. For example, you can use xilinx SystemGenerator to generate a netlist for FPGA implementation from a model specified by using Matlab/Simulink.