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142 Threads found on edaboard.com: Xilinx System Generator
Hello there, I have an image processing design developed in Xiinx system generator and i have exported it as an IP core. But i have problems in sending and receiving image data in SDK. Does anyone work on these lines.? so that i can ask you further..
Have you read over and followed the instructions for installation in the SG Getting Started Guide?
Use xilinx system generator tool set and you can interface Simulink with RTL design. The other way is HDL coder from Mathworks
I am providing a voice signal to the cepstrum algorithm in xilinx system generator. Input is reaching FFT7.1 properly but it is not generating any output. What I am having on scope is just 'x' undefined output. I also took help from the following link for FFT7.1 He
how to store information (values i want to store are 5,6,7,8) in the single port ram cell of system generator in matlab simulink., what is the function of "initial vector value" in ram cell of xilinx single port ram block set ?
hello everyone, i'm using a 256 fft core in matlab system generator, i have a bandpass signals from 750mhz to 1250mhz, im sampling at a rate of 1000mhz, for 750mhz im getting a 750mhz(single peak at 192 index value), for a 1000mhz im getting 0mhz, for 1110 im getting 110mhz, 1250 mhz i'm getting 250mhz, can anybody explain how pls??
Hi... I am using FIR Compiler6.2 in xilinx system generator for a LP design..will this block read floating point values?..when i change the 'gateway in' block to floating point..error is saying that Error : Floating-point data-type is supported only for input TDATA ports of Fast Fourier Transform v8.0 block. Error occurred during
Yes it is possible. Before that you have to install vivado system design. By using xilinx system generator you can convert simulink model into HDL
Your code is only readable for xilinx system generator users that have the respective toolchain installed. To see why "doesn't work", we would need to look at the generated HDL.
Hi friends, I know something about xilinx system generator. But the problem is "i don't know how to use it" and By using system generator whether the circuit convert into HDL or not.
Hi, i want to implement different fir interpolator with interpolation rates 5,10,15 by using single fir compiler in xilinx system generator
Ever wonder why you haven't received any responses? Here let me fill you in on why I wouldn't help even if I had the .mdl file you wanted. Can somebody provide A Model of 'Canny Edge Detector' fully made in xilinx system generator. If someone worked on something non-trivial like this, it was likely: 1) fo
Hi friends, I need to know about xilinx system generator. For what purpose we are using that ?? And whether the blocks are modeled using MATLAB or xilinx.. I need to know about these things.. And also for using the system generator whether we have to install separate tool or not??? (...)
hello everyone, i am a student and got a project for "implementation of a channel equalizer for a wireless OFDM according to the IEEE 802.11a and Hiperlan/2 standard." i dont have knowledge about system level design environments for DSPs into FPGAs..,what i have is this ieee paper and nothing else, i was unable to gain knowledge on internet:
hi guys, i have project about adaptive filter, i built a model in system generator based on hldcoderlms,but when i start with first tap of filter the result between hdl coder(simulink matlab) and my model (on system generator) is incorrecrt (or i can say wrong), but i dont know why, please help me PS: if anyone has model (...)
Hi, I am trying to build the peripheral around Cortex-M0 IP core thorugh AHB-lite system. Right now I have to integrate Cortex-M0 with the DDR2 SRAM (1Gb) through AHB lite. I find on internet which shows interfacing only through core generator (MIG). Is there a way I can use xilinx core generator to interface through AHB (...)
Hello all, I need to get output of my matlab simulation on spartan 6 XC6SLX150T FPGA LCD display, steps are as follow 1) i run my simulation with xilinx 14.1 system generator, 2) i run the .xise file generated in matlab with the xilinx 14.1, 3)the program get synthesize, implemented design, generated programming file, (...)
Hi every one. I tried a lot to figure out how to implement LMS algorithm by system generator but nothing. Can you guys help me and give me some hint or simulink file for implementing LMS by system generator? I search a lot in xilinx website and I didn`t find any example? If you guys know it please address (...)
hi, I am using xilinx system generator 13.4 for DDC implementation. I am not getting output after CIC 2.0 compiler block. can any one help me how to set parameters in CIC compiler. please help me
I installed a virtual machine. My virtual machine is XP, I am using matlabr2010a and xilinx 13.1 ( system generator 13.1). I get this error when I do Hardware CO-simulation in Simulink. I can play the simulation , but when I generate Hardaware co-simuluation I get this: ERROR: A license checkout has failed for system (...)