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I would expect that the DC-DC inductor is the EMI aggressor, but DC-DCs also contain "victim" circuitry which means they can "self-harm" very easily (charge pumping Vref or FB pins, FET near-zero-current servo) which are ground referred). Seems like you know the right answer, why not whip out the Dremel and see what you get (probably more instr
Hello, Can anyone please give me some guidance to design a spice model of a transistor. For my research simulation, I need spice model of ce3512k2 transistor, however I got s parameter from vendor. They don't have any equivalent circuit model or spice model. Now I need to build that model. How can I do that? Thanks Swadesh
a 700V arc is unlikely to bridge 20mm Unfortunately not true, particularly for DC voltage where the arc doesn't self-extinguish at the next zero crossing. Once ignited by the blowing fuse wire, it can bridge considerably wider distances than 20 mm, depending on the actual short circuit current. That's why fuses have a breaking capab
Hi, I don't know about that kind of circuit, so my answer is not much use. It sounds like you've checked that there is no inrush current but fuses blowing and circuit breaker tripping sound like an over current event. Does the circuit you are making use soft start circuitry or zero crossing detector circuitry? I don't see anything like that in
I assume you are simulating your loop gain with already compensated amplifier and if it is compensated well, meaning the non-dominant pole is about 3x farther in frequency than the UGBW, then closing the loop should have a -3dB frequency pretty close to the GBW. However, from your original plot of the loop gain I see that right about 0dB crossing
Can we use BC547 or BC337 Transistor in place of 2N3904 in following zero Crossing circuit?158064
158063 Can we use BC547 or BC337 Transistor in place of 2N3904 in given zero crossing detector circuit?
Hi, I am trying to calculate how much henrys I would need for a common mode choke to attenuate an spike A total cancelling is impossible. Thus you need to consider what residual spike value you can tolerate...and you need to know how big the spike was before. Additionally you need to know the waveform if the spike...and the co
Don't mix blocking and non-blocking assignments in a edge triggered always block. Only use non-blocking assignments in clocked logic and blocking in combonational always blocks. Using blocking assignments with code like this: if(tmp_chour >= 23) // 24 hour mode? tmp_chour =
Hi, You may easily find out in your own. Simple calculations you can do: "3" is from the table, "150MHz" is from the table. (Somewhere in the center of the table) 3uF --> xc = 1 / ( 2 Pi f c) = 1 / ( 2 3.14 150 MHz 3uF) = 0.00035Ohms --> 0.35m Ohms will completely short your input signal to almost zero. It is far away from
the 1kv+ is just for transients...3 phase mains peak is just 240*sqrt(2) * sqrt(3) = 587v No, you can never get all the voltage across one fet and zero on the soon as the bottom fet has 600v on it, then the top fet is turned off. Three phase rectifier ripple is much less than single phase no big caps are needed
Hi, We want to switch eight 312W resistor load banks OFF/ON simultaneously by using eight RF receivers and one RF transmitter (because we don?t want wires all over the place). This is for load transient testing for a power supply. Can we use eight RF solutions ?QAM-RX10-433? receiver modules with one RF solutions ?QAM-TX2-433? Transmi
if (counter == 0) begin counter <= 500000000; That resets the counter every time it reaches zero. Remove that and it should count once after being reset.
Hi, I am trying to import pspice .cir file into cadence spectre and I have successively generated the schematic graph. However, when I run the simulation, some errors appear. Here are the errors 157880 Here are the settings in schematic 15788115788215
We are a midsize biotech organization with little/no internal Si design expertise that is likely to need outside design services for low-noise transimpedance amplifier arrays: 1000s of channels (possibly 10k's of channels in subsequent revs of the design), on as tight a pitch as reasonably possible. This will be Si-level design, with integrated D
I am merciful today ;-) In the schematic netlist you have only mosfets - model of channel below the gate oxide. In the layout, your p-channel mosfets are putted in the n-wells, which are an island in the p-substrate. Every n-well forms p-n junction with substrate, modeled by nwd devices added by extractor into netlist. In case, when your paramete
A possible solution could be to determine the analysis frequency based on the zero crossings and then multiply the acquired signal with sine and cosine reference functions of this frequency. MAX10 comes in different flavors SC, SA, DC, DF and DA. The "compact" types SC and DC have smaller built in flash and don't support ROM tables (initialized
The 150 ohm resistance is always in the path between the op amps, thus it is the ohmic portion of the load. As for capacitors, they present zero resistance for a brief time after a change in current flow. The definition of capacitance is that it impedes a change in voltage. An op amp output has internal resistance. There may be a certain value of
I am trying to use feedfoward compensation in multi-stage OTA for driving large capacitive load. However, it always oscillate, and PZ analysis in cadence spectre always shows RHP pole in my amplifier.. The circuit I have tried are all from journals. Here is one example https
Your timing scheme has 14 steps. Create 7 arrays named SW1(), SW2(), etc. In each array create 14 elements which contain the successive state (0 or 1) of that switch. Go through a for-next loop X=1 to 14. Examine SW1(X). If it's 1, then turn it on. If zero then turn it off. Examine SW2(X). Etc through all switches. Increment X until X=14