Search Engine www.edaboard.com

78 Threads found on edaboard.com: Zero Compensation
Hi, What does the datasheet say? It says it thas zero scale offset of max. 3LSB. wiper resistance is 50 Ohms max. *** You didnīt say what resistor value your pot is, so I assume 10k. Then the reistance step size is 10k / 255 = 39 ohms. 3LSB means 3 x 39 ohms = 117 ohms. Now add the wiper resistance: 117 ohms + 50 ohms = 167 Ohms. This sho
yes, just see the opamp circuit shown in the lt1248 datasheet.. I appreciate you use average current mode control, because with current mode control , ccm pfc circuit would need very large amount of slope compensation for when voltage is near zero average current mode control is c
Dear all, This a question regarding a regulation of DC/DC converter, I am trying to use PI controller to help tracking the output error to zero. By comparing the open loop and the closed loop diagram, it does not seem like their will be any oscillation at any point, so I am not sure where to place the pole or the zero of the PI (or should I
Attached is a folded cascode amplifier with a cascode compensation capacitors Cc. How does this circuit prevent the formation of the undesired zero (in the right half of the s-plane ) ? Please let me know a logical explanation .
Do you agree with the following ?rules? (A to D) on the checking of type 2 compensator pole and zero positions? This is with regard to a CCM, Current mode flyback with a type 2 feedback compensation network..That is, making sure it is not going to be unstable.. ?The Type 2 compensator zero MUST BE at (or very near) the same freq
Hello, On pages 212 to 217 of ?Power supply cookbook? by Brown, it goes through a type 2 error amplifier feedback compensation scheme for a CCM flyback in current mode. It discusses the placement of the error amplifier's poles and zero, but does not do this with respect to the power stage RHPZ. Why is no mention made of the RHPZ? Surely an error
Yeah your feedback compensation needs some tuning. You have a lot of ringing, but the low frequency gain is also too low. Try increasing your zero frequencies while decreasing your pole frequencies (basically reduce your k factor ).
There are some papers on No-Capacitor Feed-Forward (NCFF) compensation scheme which uses a high-frequency pole-zero doublet to obtain
I was reading an article regarding insure stability of op amp in optical application. And I do not understand the reason of below statement: "Figure 4 depicts three different scenarios for the intersection of the closed-loop response curve with the open-loop gain curve. Stability degradation will occur when fP falls outside the open-loop gain cu
Hello. I designed a half bridge converter by using tl494 chip. and so it's 2pole - 2zero compensation network. but this configuration is suitable for inverting error amp configuration not non inverting like tl494. Now I confused how to solve this problem for make circuit to be stable! Actually using a RC feedback in non inverting configuration s
If I have a switching quadrature demodulator with a differential input and I purposely set the H input at a slightly higher DC offset and the L input at a slightly lower DC offset then anytime my L.O.'s I and Q switching inputs are not each exactly 50% duty cycle it will cause my I and Q zero IF outputs to have a DC offset. If I integrate those off
Hi I wanna design an opamp (2 stage folded cascode) where can I find analysis of this opamp? I need to know poles,zeros,unity gain,... for designing? plz help me I wasnt able to find any book or paper.:cry::cry: tnx
I have some doubts if the Falstad simulator represents the OP behaviour accurately in this situation, the PSpice models usually do. The basic problem is simple, zero respectively negative phase margin in the loop gain characteristic. If the OP compensation isn't accessible for modifications, you have basically two option: - an output series
check if there is a zero in your circuit.
I read that when you try to compensate using pole-zero compensation, in case the pole and the zero are not cancelled exactly then we have pole-zero doublet and I read that it creates a problem. Could you please tell me what that problem is? Also tell me why does that happen when we have a pole zero doublet? (...)
hi,everyone! I recently learnt root locus method, but there was a problem when I applied this method to analysis the basic two stage miller compensation amplifier without zero nulling. I used two port method neglecting the compensation capacitor feedforward signal to calculate the loop gain transfer function 2. There were two LHP poles (...)
Is it possible to have poles and zeroes at the same point?
The following picture has two circuits that contain the different way of compensation for polos & zeros. As I know that the 1-st(left)one has a zero on the LHP that approximate equals gm/Cc, the 2-nd(right)one has a zero on the RHP that approximate equals gm*rds*gm/Cc. I may ask that which compensition is better? thands~ (...)
Hi, everyone! For the op-amp compensated in the way as follows, there is a RHP zero a LHP zero lower than the nondominate pole. That makes it difficult to compensate , so i wonder which position introduces the zeroes and whether there is someway to modify the zeroes to a higher position. Thanks for your advice! 63296